1. Field of Invention
The invention relates to operational amplifier input stages having essentially constant transconductance and slew rate. More particularly, it relates to an input stage that incorporates a secondary, or surrogate, differential pair of transistors that remain off during normal midrange operation but gradually replace the main differential pair of transistors when the common-mode voltage approaches the supply rails.
2. Description of Prior Art
Operational amplifiers used in low-voltage CMOS integrated-circuit processes normally require a differential input stage that can operate properly even when the common-mode voltages are near the supply rails. This is because when the common-mode input voltages are near the supply rails, they cause changes in internal bias points. This, in turn, can lead to degradation in performance of the input pair and consequently the entire amplifier.
In the past, a number of differential input stage circuits have been developed to deal with and overcome the common-mode voltage problem. Most of these circuits are based on the use of a p-channel and an n-channel complementary differential pair of transistors. Some examples follow.
Ribner, D. B. et al, IEEE Journal of Solid State Circuits, Vol. SC-19, No. 6, December 1984, pp. 919–925 describes an early technique for improving the high-frequency power-supply rejection and wide common-mode input voltage range of an operational amplifier input stage via a folded-cascode stage with internal frequency compensation and current-mirror biasing stages to produce a current-folding effect. The circuit acts to turn off an input stage that has gone toward the negative-rail to a moderate extent.
Babanezhad, J. N. et al, U.S. Pat. No. 5,006,817, issued Apr. 9, 1991 describes a CMOS operational amplifier configuration with an output stage that can swing rail-to-rail for a given amount of current. The output transistors can thus be made smaller in size while still maintaining high linear output drive capability.
Nagaraj, H., U.S. Pat. No. 5,550,510, issued Aug. 27, 1996 describes a differential amplifier having two complementary differential pairs connected for rail-to-rail common-mode input voltage range operation. A constant transconductance maintaining bias circuit is also included.
Huijsing, J. H. et al, U.S. Pat. No. 5,631,607, issued May 20, 1997 describes a transconductance control circuit in which a floating voltage source is added between complementary differential input pairs of transistors. The floating voltage source maintains the sum of the gate-source voltages of the input pairs, and therefore keeps the transconductance constant.
Huijsing, J. H. et al, U.S. Pat. No. 5,734,297, issued Mar. 31, 1998 describes a rail-to-rail input stage with constant transconductance and constant common-mode output currents. A current switch is coupled to each of the input pairs of transistors and to a voltage source.
Redman-White, W., U.S. Pat. No. 5,745,007, issued Apr. 28, 1998 describes a CMOS amplifier with a differential input which is fed to six differential pairs. The circuit operates such that regardless of the common-mode input level with respect to the supply rails, four transistors provide an output current that gives a constant transconductance and slew rate.
Wang, M. et al, IEEE Journal of Solid State Circuits, Vol. 34, No. 2, February 1999, pp. 148–156 describes a method for overlapping the transition regions of the tail currents of complementary differential n- and p-input transistor pairs to achieve constant overall transconductance.
Duque-Carrillo, J. F. et al, IEEE Journal of Solid State Circuits, Vol. 35, No. 1, January 2000, pp. 33–43 describes two rail-to-rail operational amplifier circuits for very low supply voltage operation in standard CMOS technology. The first is based on an amplifier input stage having complementary differential pairs, and it incorporates a dynamic level-shifting technique to extend the amplifier's input range up to the rails. The second circuit is an input stage based on a single differential input pair.
Our invention, like many of the prior circuits, uses main n-channel and main p-channel complementary differential pairs of transistors. Unlike any of the prior approaches, however, we incorporate a secondary complementary pair of transistors that act as a surrogate transistor pair to take over the function of the main n-channel pair under the low common-mode voltage condition. In like manner, we employ a secondary complementary pair of transistors to assume the function of the main p-channel pair under the high common-mode voltage condition.